how to find rk3568_mux_route_data meaning in reference manual

https://elixir.bootlin.com/linux ... /pinctrl-rockchip.c
in static struct rockchip_mux_route_data rk3568_mux_route_data[]
RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */


in the reference manual
uart5_sin  I SDMMC0_CMD/PWM10_M1/UART5_RX_M0/CAN0_TX_M1/GPIO2_A1_u                            GRF_GPIO2A_IOMUX_SEL_L[7:4]=4'h3
*uart5_sout O SDMMC0_CLK/TEST_CLKOUT/UART5_TX_M0/CAN0_RX_M1/GPIO2_A2_d*                   GRF_GPIO2A_IOMUX_SEL_L[11:8]=4'h3

uart5_sin  I LCDC_DEN/VOP_BT1120_D15/SPI1_CLK_M1/UART5_RX_M1/I2S1_SCLK_RX_M2/GPIO3_C3_d       GRF_GPIO3C_IOMUX_SEL_L[15:12]=4'h4
*uart5_sout O LCDC_VSYNC/VOP_BT1120_D14/SPI1_MISO_M1/UART5_TX_M1/I2S1_SDO3_M2/GPIO3_C2_d* GRF_GPIO3C_IOMUX_SEL_L[11:8]=4'h4


1. how do I find offset 0x0310
2. how do I find bit setting value for WRITE_MASK_VAL(0, 0, 0)  WRITE_MASK_VAL(0, 0, 1)

Ok i got answer~

https://elixir.bootlin.com/linux/latest/source/drivers/pinctrl/pinctrl-rockchip.c#L3536
RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */

ex1:
[RK3566 TRM part1]
3.2 Function Description
SYS_GRF 0xFDC60000

3.7 SYS_GRF Register Description
GRF_IOFUNC_SEL2 0x0308
...
...
...
Bit   Attr   Reset   Value   Description
7 RO 0x0 reserved

6 RW 0x0
pwm12_iomux_sel PWM12 IO mux selection
1'b0:M0 mux solution
1'b1:M1 mux solution

5 RO 0x0 reserved

4 RW 0x0
pwm11_iomux_sel PWM11 IO mux selection
1'b0:M0 mux solution
1'b1:M1 mux solution

3 RO 0x0 reserved 2 RW 0x0
pwm10_iomux_sel PWM10 IO mux selection
1'b0:M0 mux solution
1'b1:M1 mux solution

1 RO 0x0 reserved

0 RW 0x0
pwm9_iomux_sel PWM9 IO mux selection
1'b0:M0 mux solution
1'b1:M1 mux solution

ex2:
static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */

[RK3566 TRM part1]
PMU_GRF_SOC_CON4
Address: Operational Base + offset (0x0110)
...
...
...
Bit    Attr   Reset Value   Description
1:0   RW   0x3                pwm0_iomux_sel PWM0 IO mux selection
b00:M0 mux solution
b01:M1 mux solution
b10: Reserved
b11: Reserved