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一、产品简介

TB-RK3568X采用四核64位Cortex-A55 处理器,主频高达2.0GHz,效能有大幅提升;采用22nm先进工艺,具有低功耗高性能的特点;配置双千兆自适应RJ45以太网口,可通过双网口访问和传输内外网的数据,提高网络传输效率,满足NVR、工业网关等多网口产品需求。

TB-RK3568X核心板采用6层布线工艺,整体尺寸只有82mm×60mm,性能稳定可靠,适用于不同的应用环境。核心板通过MXM314Pin标准接口与底板连接即可形成一块完整的 AI 开发板,也可与定制开发的底板连接形成一套完整的行业应用主板,可广泛应用于嵌入式人工智能领域。TB-RK3568X开发板支持Android和Linux双系统。

二、产品优势

核心板尺寸仅82mm×60mm,紧凑尺寸的封装形式满足小型终端产品对空间的需求。

性价比高:成本低,适合中小规模用户使用。

双网口:可通过双网口访问和传输内外网的数据,提高网络传输效率

多屏异显:最多可以满足三屏异显功能

支持双系统:支持android和linux系统。

三、芯片架构

四、系统框图

五、产品尺寸

六、规格参数

6.1 核心板规格参数

SOC 系统芯片 Rockchip RK3568
CPU 中央处理器 Quad-core Cortex-A55 up to 2.0GHz
GPU 图形处理器 Mali-G52 GPU
支持OpenGL ES 1.1/2.0/3.2,OpenCL 2.0,Vulkan 1.1
内嵌高性能2D加速硬件
VPU 视频处理单元 支持4K 60fps H.265/H.264/VP9视频解码
支持1080P 100fps H.265/H.264视频编码
支持8M ISP,支持HDR
NPU 嵌入式神经网络处理器 支持0.8T算力,支持INT8,INT16,FP16运算
CPU 内存 2/4GB LPDRR4/LPDRR4x,最高可配8GB,频率高达1600MHz
NPU 内存 共享3568端ddr,根据模型大小,决定开辟多大
Storage 闪存 16/32 GB
输入电源 DC 12V/2A
系统支持 Android、Linux
PCB 规格 6 层板
核心板尺寸 82mm×60mm
接口类型 SODIMM 314P(MXM 3.0)

6.2 底板规格参数

底板尺寸 180mm×130mm
PCB 规格 4 层板
显示接口 1x HDMI2.0(Type-A)接口,支持4K/60fps输出
2x MIPI接口,支持1920*1080@60fps输出
1x eDP接口,支持2K@60fps输出
音频接口 1x 8ch I2S/TDM/PDM
1x HDMI音频输出
1x 喇叭输出
1x 耳机输出
1x 麦克风,板载音频输入
以太网 2x GMAC(10/100/1000M)
无线网络 SDIO接口,支持WIFI6 5G/2.5G,BT4.2
摄像头接口 MIPI-CSI2, 1x4-lane/2x2-lane@2.5Gbps/lane
USB 2x USB2.0 Host,Type-A
1x USB3.0 Host,Type-A
1x USB3.0 OTG
PCIe 1x 2Lanes PCIe3.0 Connector (RC Mode)
SATA 1x SATA3.0 Connector
SDMMC 1x Micro SD Card3.0
按键 1x Vol+/Recovery
1x Reset
1x Power
1x Vol-
1x Mute
调试 1x 调试串口
RTC 1x RTC
IR 1x IR
三色灯 3x LED
G-sensor 1x G-sensor
FAN 1x Fan
扩展接口 20Pin扩展接口包括:
2x ADC接口
2x I2C接口
7x GPIO口(或者3x gpio + 4x uart信号)
3x VCC电源(12V、3.3V、5V))

七、产品接口

7.1、Top面接口图

7.2、Bottom面接口图

7.3、MXM314Pin 定义

7.4接口复用简介

BT1120:将GMAC1相关引脚用于BT1120,则能实现BT1120相关输出(目前底板上没有留BT1120接口)。

PCIE:目前有1x 2Lanes PCIe3.0 Connector (RC Mode),如果想增加PCIE2.0,将MULTI_PHY2配置为PCIE模式。

SATA:目前有1x SATA3.0,也可以通过配置MULTI_PHY0、MULTI_PHY1为SATA,就能实现3x SATA3.0。

RGMII:目前有2x RGMII,如果想增加QSGMII,需要将MULTI_PHY1、MULTI_PHY2配置为QSGMII。

其他相关复用配置,具体查看官方RK3568DataSheet。

7.5接口电气特性描述

Power

Pin Num Pin net Type level tolerance
309 VCC5V0_SYS Power In 5.0V +/-10%
311 VCC5V0_SYS Power In 5.0V +/-10%
296 VCC12V_DCIN Power In 12.0V +/-10%
297 VCC12V_DCIN Power In 12.0V +/-10%
298 VCC12V_DCIN Power In 12.0V +/-10%
300 VCC12V_DCIN Power In 12.0V +/-10%
299 VCC_3V3 Power Out 3.3V +/-10%
301 VCC_3V3 Power Out 3.3V +/-10%
306 VCC3V3_SYS Power Out 3.3V +/-10%
308 VCC3V3_SYS Power Out 3.3V +/-10%
307 VCC_1V8 Power Out 1.8V +/-10%
305 VCC3V3_SD Power Out 3.3V +/-10%

WIFI/BT module interface

Pin Num Pin net Type level description
253 WIFI_WAKE_HOST_H_GPIO3_D4 In 1.8V WLAN to wake-up HOST
223 WIFI_REG_ON_H_GPIO3_D5 Out 1.8V Power up/down internal regulators
260 BT_REG_ON_H_GPIO3_A0 Out 3.3V Power up/down internal regulators
256 BT_WAKE_HOST_H_GPIO3_A1 In 3.3V Bluetooth device to wake-up HOST
254 HOST_WAKE_BT_H_GPIO3_A2 Out 3.3V HOST wake-up Bluetooth device
30 UART0_CTS_BT Out Bluetooth UART interface
28 UART0_RTS_BT In Bluetooth UART interface
32 UART0_RXD_BT Out Bluetooth UART interface
36 UART0_TXD_BT In Bluetooth UART interface
241 SDMMC2_CLK_M0 In/Out SDIO clock line
203 SDMMC2_CMD_M0 In/Out SDIO command line
211 SDMMC2_D0_M0 In/Out SDIO data line 0
209 SDMMC2_D1_M0 In/Out SDIO data line 1
215 SDMMC2_D2_M0 In/Out SDIO data line 2
249 SDMMC2_D3_M0 In/Out SDIO data line 3
262 I2S3_SCLK_M0 In/Out 3.3V
258 I2S3_LRCK_M0 In/Out 3.3V
264 I2S3_SDO_M0 Out 3.3V
266 I2S3_SDI_M0 In 3.3V
292 RK809_32KOUT_WIFI Out 3.3V 32.768KHz output for BT
130 CLK32K_OUT0_WIFI Out 3.3V 32.768KHz output for BT

TypeC(USB3) interface

Pin num Pin net Type level description
65 USB3_OTG0_DP In/Out usb
63 USB3_OTG0_DM In/Out usb
77 USB3_OTG0_SSTXP In/Out usb
75 USB3_OTG0_SSTXN In/Out usb
71 USB3_OTG0_SSRXP In/Out usb
69 USB3_OTG0_SSRXN In/Out usb
83 USB3_HOST1_DP In/Out usb
81 USB3_HOST1_DM In/Out usb
95 USB3_HOST1_SSTXP In/Out usb
93 USB3_HOST1_SSTXN In/Out usb
89 USB3_HOST1_SSRXP In/Out usb
87 USB3_HOST1_SSRXN In/Out usb
9 USB2_HOST2_DP In/Out usb
11 USB2_HOST2_DM In/Out usb
3 USB2_HOST3_DP In/Out usb
5 USB2_HOST3_DM In/Out usb
57 USB3_OTG0_VBUSDET In usb usb dector
59 USB3_OTG0_ID In/Out usb interrupt
127 USB_OTG_PWREN_H_GPIO0_A5 Out 3.3V 5V output power enable
123 USB_HOST_PWREN_H_GPIO0_A6 Out 3.3V 5V output power enable

DMMC interface

Pin num Pin net Type level
54 SDMMC0_CLK Out 1.8V/3.3V
44 SDMMC0_CMD Out 1.8V/3.3V
117 SDMMC0_DET_L In 3.3V
48 SDMMC0_D0 In/Out 1.8V/3.3V
52 SDMMC0_D1 In/Out 1.8V/3.3V
50 SDMMC0_D2 In/Out 1.8V/3.3V
46 SDMMC0_D3 In/Out 1.8V/3.3V

Note: SDMMC interface level 1V8/3V0 Auto switch

HDMI out interface

Pin num Pin net Type level description
230 HDMITX_SCL Out 3.3V I2C interface
232 HDMITX_SDA In/Out 3.3V I2C interface
234 HDMI_CEC In 3.3V HDMI CEC
161 HDMI_PORT_HPD In 1.8V HDMI HPD
156 HDMI_TXCP Out HDMI_TX HDMI Tx CLK Line
158 HDMI_TXCN Out HDMI Tx CLK Line
152 HDMI_TX0N Out HDMI Tx Data Line
150 HDMI_TX0P Out HDMI Tx Data Line
140 HDMI_TX2N Out HDMI Tx Data Line
130 HDMI_TX2P Out HDMI Tx Data Line
144 HDMI_TX1P Out HDMI Tx Data Line
146 HDMI_TX1N Out HDMI Tx Data Line

Note:

  1. I2C level need match with HDMI 5V Level,external circuit is needed.

  2. HDMI_CEC,external Pull-up is needed.

MIPI_TX interface

Pin num Pin net Type level description
155 TP_INT_L_GPIO0_B5 In 3.3V TP interrupt
153 TP_RST_L_GPIO0_B6 Out 3.3V TP reset
137 LCD0_BL_PWM4 Out 3.3V LCD BackLight PWM
143 LCD0_PWREN_H_GPIO0_C7 Out 3.3V MIPI Power Enable
159 I2C1_SDA_TP In/Out 3.3V TP I2C interface
157 I2C1_SCL_TP Out 3.3V TP I2C interface
188 MIPI_TX0_D3P Out MIPI_TX MIPI Tx Date line
186 MIPI_TX0_D3N Out MIPI_TX MIPI Tx Date line
182 MIPI_TX0_D2P Out MIPI_TX MIPI Tx Date line
180 MIPI_TX0_D2N Out MIPI_TX MIPI Tx Date line
174 MIPI_TX0_CLKN Out MIPI_TX MIPI Tx CLK line
176 MIPI_TX0_CLKP Out MIPI_TX MIPI Tx CLK line
170 MIPI_TX0_D1P Out MIPI_TX MIPI Tx Date line
168 MIPI_TX0_D1N Out MIPI_TX MIPI Tx Date line
162 MIPI_TX0_D0N Out MIPI_TX MIPI Tx Date line
164 MIPI_TX0_D0P Out MIPI_TX MIPI Tx Date line
217 LCD0_RST_L_GPIO3_B5 Out 3.3V
47 SARADC_VIN2_LCD_ID In 1.8V

MIPI_RX interface

Pin num Pin net Type level description
207 CAMERA0_PDN_L_GPIO4_B4 Out 1.8V
235 CAMERA1_PDN_L_GPIO4_B5 Out 1.8V
199 MIPICAM1_RST_L_GPIO4_C6 Out 3.3V
125 MIPICAM0_RST_L_GPIO0_D6 Out 1.8V
237 I2C4_SDA_M0 In/Out 1.8V CAMERA I2C interface
269 I2C4_SCL_M0 In/Out 1.8V CAMERA I2C interface
222 MIPI_CSI_RX_D3P In MIPI_RX MIPI Rx Date line
224 MIPI_CSI_RX_D3N In MIPI_RX MIPI Rx Date line
216 MIPI_CSI_RX_D2P In MIPI_RX MIPI Rx Date line
218 MIPI_CSI_RX_D2N In MIPI_RX MIPI Rx Date line
206 MIPI_CSI_RX_CLK0N In MIPI_RX MIPI Rx CLK line
204 MIPI_CSI_RX_CLK0P In MIPI_RX MIPI Rx CLK line
212 MIPI_CSI_RX_CLK1N MIPI_RX
210 MIPI_CSI_RX_CLK1P MIPI_RX
198 MIPI_CSI_RX_D1P In MIPI_RX MIPI Rx Date line
200 MIPI_CSI_RX_D1N In MIPI_RX MIPI Rx Date line
194 MIPI_CSI_RX_D0N In MIPI_RX MIPI Rx Date line
192 MIPI_CSI_RX_D0P In MIPI_RX MIPI Rx Date line
135 DVP_PWREN0_H_GPIO0_C1 Out 3.3V
219 PWM14_M0 Out 3.3V
134 REFCLK_OUT_CAM Out 3.3V
239 CIF_CLKOUT(GPIO4_C0) Out 1.8V

EDP interface

Pin num Pin net Type level description
155 TP_INT_L_GPIO0_B5 In 1.8V edp TP interrupt
153 TP_RST_L_GPIO0_B6 Out 1.8V edp TP Reset
137 LCD0_BL_PWM4 Out 1.8V LCD BackLight enable
133 EDP_HPDIN_M1 In 3.3V EDP HPD
LCD_PWREN_H Out 1.8V LCD_PWREN_H
143 LCD0_PWREN_H_GPIO0_C7 Out 3.3V LCD BackLight control
217 LCD0_RST_L_GPIO3_B5 Out 3.3V RST control
47 SARADC_VIN2_LCD_ID In 1.8V ID
159 I2C1_SDA_TP In/Out 3.3V I2C interface for TP
157 I2C1_SCL_TP Out 3.3V I2C interface for TP
78 EDP_TX_D3N Out EDP_TX EDP Tx Data Line
76 EDP_TX_D3P Out EDP_TX EDP Tx Data Line
72 EDP_TX_D2N Out EDP_TX EDP Tx Data Line
70 EDP_TX_D2P Out EDP_TX EDP Tx Data Line
66 EDP_TX_D1N Out EDP_TX EDP Tx Data Line
64 EDP_TX_D1P Out EDP_TX EDP Tx Data Line
60 EDP_TX_D0N Out EDP_TX EDP Tx Data Line
58 EDP_TX_D0P Out EDP_TX EDP Tx Data Line
84 EDP_TX_AUXN Out EDP_TX EDP AUX Line
82 EDP_TX_AUXP Out EDP_TX EDP AUX Line

Note:

  1. LCD_BL_PWM share with MIPI_TX.

  2. I2C interface shared with MIPI_TX.

    MAC0 interface

Pin num Pin net Type level description
40 GMAC0_MDIO In/Out 1.8V in/out of management data
42 GMAC0_MDC Out 1.8V management data clock
242 GMAC0_RSTn_GPIO2_D3 Out 3.3V PHY reset
34 GMAC0_MCLKINOUT IN 1.8V Clock From PHY to MAC
26 ETH0_REFCLKO_25M IN 1.8V 25M CLK
22 GMAC0_TXEN Out MAC TX &MAC RX MAC Tx CTRL signal
8 GMAC0_TXD3 Out MAC TX &MAC RX MAC TX data3
6 GMAC0_TXD2 Out MAC TX &MAC RX MAC TX data2
20 GMAC0_TXD1 Out MAC TX &MAC RX MAC TX data1
18 GMAC0_TXD0 Out MAC TX &MAC RX MAC TX data0
10 GMAC0_TXCLK Out MAC TX &MAC RX Tx ref CLK depend on speed
14 GMAC0_RXD3 In MAC TX &MAC RX MAC RX data3
12 GMAC0_RXD2 In MAC TX &MAC RX MAC RX data2
38 GMAC0_RXD1 In MAC TX &MAC RX MAC RX data1
16 GMAC0_RXD0 In MAC TX &MAC RX MAC RX data0
4 GMAC0_RXCLK In MAC TX &MAC RX RX ref CLK from RX data stream
24 GMAC0_RXDV_CRS In MAC TX &MAC RX MAC Rx CTRL signal
236 GMAC0_INT/PMEB_GPIO2_D2 In 3.3V PHY interrupt signal

MAC1 interface

Pin num Pin net Type level description
243 GMAC1_MDIO_M1 In/Out 1.8V in/out of management data
245 GMAC1_MDC_M1 Out 1.8V management data clock
238 GMAC1_RSTn_GPIO2_D1 Out 3.3V PHY reset
267 GMAC1_MCLKINOUT_M1 IN 1.8V Clock From PHY to MAC
270 ETH1_REFCLKO_25M_M0 IN 3.3V 25M CLK
259 GMAC1_TXEN_M1 Out MAC TX&MAC RX MAC Tx CTRL signal
231 GMAC1_TXD3_M1 Out MAC TX&MAC RX MAC TX data3
233 GMAC1_TXD2_M1 Out MAC TX&MAC RX MAC TX data2
257 GMAC1_TXD1_M1 Out MAC TX&MAC RX MAC TX data1
255 GMAC1_TXD0_M1 Out MAC TX&MAC RX MAC TX data0
225 GMAC1_TXCLK_M1 Out MAC TX&MAC RX Tx ref CLK depend on speed
227 GMAC1_RXD3_M1 In MAC TX&MAC RX MAC RX data3
251 GMAC1_RXD2_M1 In MAC TX&MAC RX MAC RX data2
247 GMAC1_RXD1_M1 In MAC TX&MAC RX MAC RX data1
265 GMAC1_RXD0_M1 In MAC TX&MAC RX MAC RX data0
229 GMAC1_RXCLK_M1 In MAC TX&MAC RX RX ref CLK from RX data stream
261 GMAC1_RXDV_CRS_M1 In MAC TX&MAC RX MAC Rx CTRL signal
236 GMAC1_INT/PMEB_GPIO2_D0 In 3.3V PHY interrupt signal

Audio interface

Pin num Pin net Type level description
23 I2S1_SCLK OUT I2S 1.8V
39 I2S1_LRCK_RX IN I2S 1.8V
15 I2S1_LRCK_TX OUT I2S 1.8V
19 I2S_CLK 0UT I2S 1.8V
17 I2S1_SDO0 OUT I2S 1.8V
31 I2C3_SDA In/Out 1.8V AUDIO I2S
33 I2C3_SCL In/Out 1.8V AUDIO I2S
221 HP_DET_RK809(GPIO3_C3) In 3.3V Headphone detect
MIC2_IN In analog mic2 input
43 ADC1_HP_HOOK In 1.8V ADC used for Hook
283 HPL_OUT Out analog HP left
287 HPR_OUT Out analog HP right
285 HP_SNS GND GND
205 HP_DET_L_GPIO3_C2 In 3.3V Headphone detect

MIC interface

Pin num Pin net Type level description
289 MIC1_INN In analog Mic1 input
291 MIC1_INP In analog Mic2 input

Speaker interface

Pin num Pin net Type level description
281 SPKN_OUT Out analog connect SPK,1.3W max
279 SPKP_OUT Out analog connect SPK,1.3W max

PCIE interface

Pin num Pin net Type level description
248 PCIE30X2_CLKREQn_M1 Out 3.3V
244 PCIE30X2_WAKEn_M1 Out 3.3V
246 PCIE30X2_PERSTn_M1 Out 3.3V
119 PCIE_PWREN_H_GPIO0_D4 Out 1.8V
268 PCIECLKIC_OE_H_GPIO3_A7 Out 3.3V
250 PCIE30X2_PRSNT_L_GPIO2_D7 Out 3.3V PCIE reset
126 PCIE30_RX1P In PCIE_TX & PCIE_RX PCIE Rx Data Line
124 PCIE30_RX1N In PCIE_TX & PCIE_RX PCIE Rx Data Line
112 PCIE30_TX1N Out PCIE_TX & PCIE_RX PCIE Tx Data Line
114 PCIE30_TX1P Out PCIE_TX & PCIE_RX PCIE Tx Data Line
118 PCIE30_RX0N In PCIE_TX & PCIE_RX PCIE Rx Data Line
120 PCIE30_RX0P In PCIE_TX & PCIE_RX PCIE Rx Data Line
108 PCIE30_TX0P Out PCIE_TX & PCIE_RX PCIE Tx Data Line
106 PCIE30_TX0N Out PCIE_TX & PCIE_RX PCIE Tx Data Line
102 PCIE30_REFCLKP_IN Out PCIE_TX & PCIE_RX PCIE CLK Line
100 PCIE30_REFCLKN_IN Out PCIE_TX & PCIE_RX PCIE CLK Line
113 PCIE20_REFCLKP Out PCIE_TX & PCIE_RX PCIE CLK Line
111 PCIE20_REFCLKN Out PCIE_TX & PCIE_RX PCIE CLK Line
101 MULTI_PHY0_REFCLKP Out PCIE_TX & PCIE_RX PCIE CLK Line
99 MULTI_PHY0_REFCLKN Out PCIE_TX & PCIE_RX PCIE CLK Line
107 MULTI_PHY1_REFCLKP Out PCIE_TX & PCIE_RX PCIE CLK Line
105 MULTI_PHY1_REFCLKN Out PCIE_TX & PCIE_RX PCIE CLK Line
112 PCIE30_TX1N Out PCIE_TX & PCIE_RX PCIE Tx Data Line
114 PCIE30_TX1P Out PCIE_TX & PCIE_RX PCIE Tx Data Line
126 PCIE30_RX1P In PCIE_TX & PCIE_RX PCIE Rx Data Line
124 PCIE30_RX1N In PCIE_TX & PCIE_RX PCIE Rx Data Line

SATA interface

Pin num Pin net Type level description
88 SATA2_TXP In/Out Sata sata TRx Date line
90 SATA2_TXN In/Out Sata sata TRx Date line
94 SATA2_RXP In/Out Sata sata TRx Date line
96 SATA2_RXN In/Out Sata sata TRx Date line
195 SATA2_ACT_LED Out 3.3V GPIO

Other

pin num Pin net Type level description
49 SARADC_VIN0_KEY/RECOVERY In 1.8V Recovery pin,connect key
271 RESET_KEY In 1.8V ADC input,connect key
275 POWER_KEY In 1.8V Power pin,connect key
129 RTCIC_INT_L_GPIO0_D3 In 1.8V GPIO,default input
145 PWM7_IR In 3.3V IR
197 SYSTEM_WORK_LED1 Out 3.3V GPIO,
193 SYSTEM_WORK_LED2 Out 3.3V GPIO,
201 SYSTEM_WORK_LED3 Out 3.3V GPIO
273 EXT_EN Out
278 I2C5_SCL_M0 In/Out 3.3V I2C
280 I2C5_SDA_M0 In/Out 3.3V I2C
151 UART2_TX_M0_DEBUG In 3.3V UART
149 UART2_RX_M0_DEBUG Out 3.3V UART
284 GSENSOR_INT_L_GPIO3_C1 Out 3.3V
228 GPIO4_D2 Out 3.3V FAN_CTRL

Extensible 20 pin interface(UART,GPIO,ADC,I2C)

Pin num Pin net Type level description
139 WORKING_LEDEN_H_GPIO0_C0 Out 3.3V GPIO,default output Low
141 CPU_AVS/CPU_DVS_PWM0_M0 Out 3.3V GPIO,default output Low
53 SARADC_VIN4 In 1.8V ADC input
45 SARADC_VIN5 In 1.8V ADC input
51 SARADC_VIN6 In 1.8V ADC input
274 UART4_RX_M1 In 1.8V debug interface
276 UART4_TX_M1 Out 1.8V debug interface
286 UART3_RX_M1 In 3.3V UART interface
282 UART3_TX_M1 Out 3.3V UART interface
33 I2C3_SCL In/Out 1.8V I2C interface
31 I2C3_SDA In/Out 1.8V I2C interface
311 VCC5V0_SYS Out
306 VCC3V3_SYS Out
296 VCC12V_DCIN Out
290 SPDIF_TX_M1 Out 3.3V

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